717 lines
21 KiB
Go
717 lines
21 KiB
Go
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// Copyright 2015 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// Package arch defines architecture-specific information and support functions.
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package arch
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import (
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"github.com/twitchyliquid64/golang-asm/obj"
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"github.com/twitchyliquid64/golang-asm/obj/arm"
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"github.com/twitchyliquid64/golang-asm/obj/arm64"
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"github.com/twitchyliquid64/golang-asm/obj/mips"
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"github.com/twitchyliquid64/golang-asm/obj/ppc64"
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"github.com/twitchyliquid64/golang-asm/obj/riscv"
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"github.com/twitchyliquid64/golang-asm/obj/s390x"
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"github.com/twitchyliquid64/golang-asm/obj/wasm"
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"github.com/twitchyliquid64/golang-asm/obj/x86"
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"fmt"
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"strings"
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)
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// Pseudo-registers whose names are the constant name without the leading R.
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const (
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RFP = -(iota + 1)
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RSB
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RSP
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RPC
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)
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// Arch wraps the link architecture object with more architecture-specific information.
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type Arch struct {
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*obj.LinkArch
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// Map of instruction names to enumeration.
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Instructions map[string]obj.As
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// Map of register names to enumeration.
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Register map[string]int16
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// Table of register prefix names. These are things like R for R(0) and SPR for SPR(268).
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RegisterPrefix map[string]bool
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// RegisterNumber converts R(10) into arm.REG_R10.
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RegisterNumber func(string, int16) (int16, bool)
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// Instruction is a jump.
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IsJump func(word string) bool
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}
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// nilRegisterNumber is the register number function for architectures
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// that do not accept the R(N) notation. It always returns failure.
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func nilRegisterNumber(name string, n int16) (int16, bool) {
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return 0, false
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}
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// Set configures the architecture specified by GOARCH and returns its representation.
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// It returns nil if GOARCH is not recognized.
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func Set(GOARCH string) *Arch {
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switch GOARCH {
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case "386":
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return archX86(&x86.Link386)
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case "amd64":
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return archX86(&x86.Linkamd64)
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case "arm":
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return archArm()
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case "arm64":
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return archArm64()
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case "mips":
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return archMips(&mips.Linkmips)
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case "mipsle":
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return archMips(&mips.Linkmipsle)
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case "mips64":
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return archMips64(&mips.Linkmips64)
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case "mips64le":
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return archMips64(&mips.Linkmips64le)
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case "ppc64":
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return archPPC64(&ppc64.Linkppc64)
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case "ppc64le":
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return archPPC64(&ppc64.Linkppc64le)
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case "riscv64":
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return archRISCV64()
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case "s390x":
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return archS390x()
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case "wasm":
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return archWasm()
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}
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return nil
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}
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func jumpX86(word string) bool {
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return word[0] == 'J' || word == "CALL" || strings.HasPrefix(word, "LOOP") || word == "XBEGIN"
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}
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func jumpRISCV(word string) bool {
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switch word {
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case "BEQ", "BEQZ", "BGE", "BGEU", "BGEZ", "BGT", "BGTU", "BGTZ", "BLE", "BLEU", "BLEZ",
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"BLT", "BLTU", "BLTZ", "BNE", "BNEZ", "CALL", "JAL", "JALR", "JMP":
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return true
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}
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return false
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}
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func jumpWasm(word string) bool {
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return word == "JMP" || word == "CALL" || word == "Call" || word == "Br" || word == "BrIf"
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}
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func archX86(linkArch *obj.LinkArch) *Arch {
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register := make(map[string]int16)
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// Create maps for easy lookup of instruction names etc.
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for i, s := range x86.Register {
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register[s] = int16(i + x86.REG_AL)
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}
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// Pseudo-registers.
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register["SB"] = RSB
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register["FP"] = RFP
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register["PC"] = RPC
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// Register prefix not used on this architecture.
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instructions := make(map[string]obj.As)
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for i, s := range obj.Anames {
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instructions[s] = obj.As(i)
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}
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for i, s := range x86.Anames {
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if obj.As(i) >= obj.A_ARCHSPECIFIC {
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instructions[s] = obj.As(i) + obj.ABaseAMD64
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}
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}
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// Annoying aliases.
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instructions["JA"] = x86.AJHI /* alternate */
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instructions["JAE"] = x86.AJCC /* alternate */
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instructions["JB"] = x86.AJCS /* alternate */
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instructions["JBE"] = x86.AJLS /* alternate */
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instructions["JC"] = x86.AJCS /* alternate */
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instructions["JCC"] = x86.AJCC /* carry clear (CF = 0) */
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instructions["JCS"] = x86.AJCS /* carry set (CF = 1) */
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instructions["JE"] = x86.AJEQ /* alternate */
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instructions["JEQ"] = x86.AJEQ /* equal (ZF = 1) */
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instructions["JG"] = x86.AJGT /* alternate */
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instructions["JGE"] = x86.AJGE /* greater than or equal (signed) (SF = OF) */
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instructions["JGT"] = x86.AJGT /* greater than (signed) (ZF = 0 && SF = OF) */
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instructions["JHI"] = x86.AJHI /* higher (unsigned) (CF = 0 && ZF = 0) */
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instructions["JHS"] = x86.AJCC /* alternate */
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instructions["JL"] = x86.AJLT /* alternate */
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instructions["JLE"] = x86.AJLE /* less than or equal (signed) (ZF = 1 || SF != OF) */
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instructions["JLO"] = x86.AJCS /* alternate */
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instructions["JLS"] = x86.AJLS /* lower or same (unsigned) (CF = 1 || ZF = 1) */
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instructions["JLT"] = x86.AJLT /* less than (signed) (SF != OF) */
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instructions["JMI"] = x86.AJMI /* negative (minus) (SF = 1) */
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instructions["JNA"] = x86.AJLS /* alternate */
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instructions["JNAE"] = x86.AJCS /* alternate */
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instructions["JNB"] = x86.AJCC /* alternate */
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instructions["JNBE"] = x86.AJHI /* alternate */
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instructions["JNC"] = x86.AJCC /* alternate */
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instructions["JNE"] = x86.AJNE /* not equal (ZF = 0) */
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instructions["JNG"] = x86.AJLE /* alternate */
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instructions["JNGE"] = x86.AJLT /* alternate */
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instructions["JNL"] = x86.AJGE /* alternate */
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instructions["JNLE"] = x86.AJGT /* alternate */
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instructions["JNO"] = x86.AJOC /* alternate */
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instructions["JNP"] = x86.AJPC /* alternate */
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instructions["JNS"] = x86.AJPL /* alternate */
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instructions["JNZ"] = x86.AJNE /* alternate */
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instructions["JO"] = x86.AJOS /* alternate */
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instructions["JOC"] = x86.AJOC /* overflow clear (OF = 0) */
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instructions["JOS"] = x86.AJOS /* overflow set (OF = 1) */
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instructions["JP"] = x86.AJPS /* alternate */
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instructions["JPC"] = x86.AJPC /* parity clear (PF = 0) */
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instructions["JPE"] = x86.AJPS /* alternate */
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instructions["JPL"] = x86.AJPL /* non-negative (plus) (SF = 0) */
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instructions["JPO"] = x86.AJPC /* alternate */
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instructions["JPS"] = x86.AJPS /* parity set (PF = 1) */
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instructions["JS"] = x86.AJMI /* alternate */
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instructions["JZ"] = x86.AJEQ /* alternate */
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instructions["MASKMOVDQU"] = x86.AMASKMOVOU
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instructions["MOVD"] = x86.AMOVQ
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instructions["MOVDQ2Q"] = x86.AMOVQ
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instructions["MOVNTDQ"] = x86.AMOVNTO
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instructions["MOVOA"] = x86.AMOVO
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instructions["PSLLDQ"] = x86.APSLLO
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instructions["PSRLDQ"] = x86.APSRLO
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instructions["PADDD"] = x86.APADDL
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return &Arch{
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LinkArch: linkArch,
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Instructions: instructions,
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Register: register,
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RegisterPrefix: nil,
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RegisterNumber: nilRegisterNumber,
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IsJump: jumpX86,
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}
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}
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func archArm() *Arch {
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register := make(map[string]int16)
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// Create maps for easy lookup of instruction names etc.
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// Note that there is no list of names as there is for x86.
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for i := arm.REG_R0; i < arm.REG_SPSR; i++ {
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register[obj.Rconv(i)] = int16(i)
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}
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// Avoid unintentionally clobbering g using R10.
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delete(register, "R10")
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register["g"] = arm.REG_R10
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for i := 0; i < 16; i++ {
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register[fmt.Sprintf("C%d", i)] = int16(i)
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}
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// Pseudo-registers.
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register["SB"] = RSB
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register["FP"] = RFP
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register["PC"] = RPC
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register["SP"] = RSP
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registerPrefix := map[string]bool{
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"F": true,
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"R": true,
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}
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// special operands for DMB/DSB instructions
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register["MB_SY"] = arm.REG_MB_SY
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register["MB_ST"] = arm.REG_MB_ST
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register["MB_ISH"] = arm.REG_MB_ISH
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register["MB_ISHST"] = arm.REG_MB_ISHST
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register["MB_NSH"] = arm.REG_MB_NSH
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register["MB_NSHST"] = arm.REG_MB_NSHST
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register["MB_OSH"] = arm.REG_MB_OSH
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register["MB_OSHST"] = arm.REG_MB_OSHST
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instructions := make(map[string]obj.As)
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for i, s := range obj.Anames {
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instructions[s] = obj.As(i)
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}
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for i, s := range arm.Anames {
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if obj.As(i) >= obj.A_ARCHSPECIFIC {
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instructions[s] = obj.As(i) + obj.ABaseARM
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}
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}
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// Annoying aliases.
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instructions["B"] = obj.AJMP
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instructions["BL"] = obj.ACALL
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// MCR differs from MRC by the way fields of the word are encoded.
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// (Details in arm.go). Here we add the instruction so parse will find
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// it, but give it an opcode number known only to us.
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instructions["MCR"] = aMCR
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return &Arch{
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LinkArch: &arm.Linkarm,
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Instructions: instructions,
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Register: register,
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RegisterPrefix: registerPrefix,
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RegisterNumber: armRegisterNumber,
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IsJump: jumpArm,
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}
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}
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func archArm64() *Arch {
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register := make(map[string]int16)
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// Create maps for easy lookup of instruction names etc.
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// Note that there is no list of names as there is for 386 and amd64.
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register[obj.Rconv(arm64.REGSP)] = int16(arm64.REGSP)
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for i := arm64.REG_R0; i <= arm64.REG_R31; i++ {
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register[obj.Rconv(i)] = int16(i)
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}
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// Rename R18 to R18_PLATFORM to avoid accidental use.
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register["R18_PLATFORM"] = register["R18"]
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delete(register, "R18")
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for i := arm64.REG_F0; i <= arm64.REG_F31; i++ {
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register[obj.Rconv(i)] = int16(i)
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}
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for i := arm64.REG_V0; i <= arm64.REG_V31; i++ {
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register[obj.Rconv(i)] = int16(i)
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}
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// System registers.
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for i := 0; i < len(arm64.SystemReg); i++ {
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register[arm64.SystemReg[i].Name] = arm64.SystemReg[i].Reg
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}
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register["LR"] = arm64.REGLINK
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register["DAIFSet"] = arm64.REG_DAIFSet
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register["DAIFClr"] = arm64.REG_DAIFClr
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register["PLDL1KEEP"] = arm64.REG_PLDL1KEEP
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register["PLDL1STRM"] = arm64.REG_PLDL1STRM
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register["PLDL2KEEP"] = arm64.REG_PLDL2KEEP
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register["PLDL2STRM"] = arm64.REG_PLDL2STRM
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register["PLDL3KEEP"] = arm64.REG_PLDL3KEEP
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register["PLDL3STRM"] = arm64.REG_PLDL3STRM
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register["PLIL1KEEP"] = arm64.REG_PLIL1KEEP
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register["PLIL1STRM"] = arm64.REG_PLIL1STRM
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register["PLIL2KEEP"] = arm64.REG_PLIL2KEEP
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register["PLIL2STRM"] = arm64.REG_PLIL2STRM
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register["PLIL3KEEP"] = arm64.REG_PLIL3KEEP
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register["PLIL3STRM"] = arm64.REG_PLIL3STRM
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register["PSTL1KEEP"] = arm64.REG_PSTL1KEEP
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register["PSTL1STRM"] = arm64.REG_PSTL1STRM
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register["PSTL2KEEP"] = arm64.REG_PSTL2KEEP
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register["PSTL2STRM"] = arm64.REG_PSTL2STRM
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register["PSTL3KEEP"] = arm64.REG_PSTL3KEEP
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register["PSTL3STRM"] = arm64.REG_PSTL3STRM
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// Conditional operators, like EQ, NE, etc.
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register["EQ"] = arm64.COND_EQ
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register["NE"] = arm64.COND_NE
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register["HS"] = arm64.COND_HS
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register["CS"] = arm64.COND_HS
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register["LO"] = arm64.COND_LO
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register["CC"] = arm64.COND_LO
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register["MI"] = arm64.COND_MI
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register["PL"] = arm64.COND_PL
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register["VS"] = arm64.COND_VS
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register["VC"] = arm64.COND_VC
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register["HI"] = arm64.COND_HI
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register["LS"] = arm64.COND_LS
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register["GE"] = arm64.COND_GE
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register["LT"] = arm64.COND_LT
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register["GT"] = arm64.COND_GT
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register["LE"] = arm64.COND_LE
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register["AL"] = arm64.COND_AL
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register["NV"] = arm64.COND_NV
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// Pseudo-registers.
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register["SB"] = RSB
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register["FP"] = RFP
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register["PC"] = RPC
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register["SP"] = RSP
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// Avoid unintentionally clobbering g using R28.
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delete(register, "R28")
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register["g"] = arm64.REG_R28
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registerPrefix := map[string]bool{
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"F": true,
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"R": true,
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"V": true,
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}
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instructions := make(map[string]obj.As)
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||
|
|
for i, s := range obj.Anames {
|
||
|
|
instructions[s] = obj.As(i)
|
||
|
|
}
|
||
|
|
for i, s := range arm64.Anames {
|
||
|
|
if obj.As(i) >= obj.A_ARCHSPECIFIC {
|
||
|
|
instructions[s] = obj.As(i) + obj.ABaseARM64
|
||
|
|
}
|
||
|
|
}
|
||
|
|
// Annoying aliases.
|
||
|
|
instructions["B"] = arm64.AB
|
||
|
|
instructions["BL"] = arm64.ABL
|
||
|
|
|
||
|
|
return &Arch{
|
||
|
|
LinkArch: &arm64.Linkarm64,
|
||
|
|
Instructions: instructions,
|
||
|
|
Register: register,
|
||
|
|
RegisterPrefix: registerPrefix,
|
||
|
|
RegisterNumber: arm64RegisterNumber,
|
||
|
|
IsJump: jumpArm64,
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
func archPPC64(linkArch *obj.LinkArch) *Arch {
|
||
|
|
register := make(map[string]int16)
|
||
|
|
// Create maps for easy lookup of instruction names etc.
|
||
|
|
// Note that there is no list of names as there is for x86.
|
||
|
|
for i := ppc64.REG_R0; i <= ppc64.REG_R31; i++ {
|
||
|
|
register[obj.Rconv(i)] = int16(i)
|
||
|
|
}
|
||
|
|
for i := ppc64.REG_F0; i <= ppc64.REG_F31; i++ {
|
||
|
|
register[obj.Rconv(i)] = int16(i)
|
||
|
|
}
|
||
|
|
for i := ppc64.REG_V0; i <= ppc64.REG_V31; i++ {
|
||
|
|
register[obj.Rconv(i)] = int16(i)
|
||
|
|
}
|
||
|
|
for i := ppc64.REG_VS0; i <= ppc64.REG_VS63; i++ {
|
||
|
|
register[obj.Rconv(i)] = int16(i)
|
||
|
|
}
|
||
|
|
for i := ppc64.REG_CR0; i <= ppc64.REG_CR7; i++ {
|
||
|
|
register[obj.Rconv(i)] = int16(i)
|
||
|
|
}
|
||
|
|
for i := ppc64.REG_MSR; i <= ppc64.REG_CR; i++ {
|
||
|
|
register[obj.Rconv(i)] = int16(i)
|
||
|
|
}
|
||
|
|
register["CR"] = ppc64.REG_CR
|
||
|
|
register["XER"] = ppc64.REG_XER
|
||
|
|
register["LR"] = ppc64.REG_LR
|
||
|
|
register["CTR"] = ppc64.REG_CTR
|
||
|
|
register["FPSCR"] = ppc64.REG_FPSCR
|
||
|
|
register["MSR"] = ppc64.REG_MSR
|
||
|
|
// Pseudo-registers.
|
||
|
|
register["SB"] = RSB
|
||
|
|
register["FP"] = RFP
|
||
|
|
register["PC"] = RPC
|
||
|
|
// Avoid unintentionally clobbering g using R30.
|
||
|
|
delete(register, "R30")
|
||
|
|
register["g"] = ppc64.REG_R30
|
||
|
|
registerPrefix := map[string]bool{
|
||
|
|
"CR": true,
|
||
|
|
"F": true,
|
||
|
|
"R": true,
|
||
|
|
"SPR": true,
|
||
|
|
}
|
||
|
|
|
||
|
|
instructions := make(map[string]obj.As)
|
||
|
|
for i, s := range obj.Anames {
|
||
|
|
instructions[s] = obj.As(i)
|
||
|
|
}
|
||
|
|
for i, s := range ppc64.Anames {
|
||
|
|
if obj.As(i) >= obj.A_ARCHSPECIFIC {
|
||
|
|
instructions[s] = obj.As(i) + obj.ABasePPC64
|
||
|
|
}
|
||
|
|
}
|
||
|
|
// Annoying aliases.
|
||
|
|
instructions["BR"] = ppc64.ABR
|
||
|
|
instructions["BL"] = ppc64.ABL
|
||
|
|
|
||
|
|
return &Arch{
|
||
|
|
LinkArch: linkArch,
|
||
|
|
Instructions: instructions,
|
||
|
|
Register: register,
|
||
|
|
RegisterPrefix: registerPrefix,
|
||
|
|
RegisterNumber: ppc64RegisterNumber,
|
||
|
|
IsJump: jumpPPC64,
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
func archMips(linkArch *obj.LinkArch) *Arch {
|
||
|
|
register := make(map[string]int16)
|
||
|
|
// Create maps for easy lookup of instruction names etc.
|
||
|
|
// Note that there is no list of names as there is for x86.
|
||
|
|
for i := mips.REG_R0; i <= mips.REG_R31; i++ {
|
||
|
|
register[obj.Rconv(i)] = int16(i)
|
||
|
|
}
|
||
|
|
|
||
|
|
for i := mips.REG_F0; i <= mips.REG_F31; i++ {
|
||
|
|
register[obj.Rconv(i)] = int16(i)
|
||
|
|
}
|
||
|
|
for i := mips.REG_M0; i <= mips.REG_M31; i++ {
|
||
|
|
register[obj.Rconv(i)] = int16(i)
|
||
|
|
}
|
||
|
|
for i := mips.REG_FCR0; i <= mips.REG_FCR31; i++ {
|
||
|
|
register[obj.Rconv(i)] = int16(i)
|
||
|
|
}
|
||
|
|
register["HI"] = mips.REG_HI
|
||
|
|
register["LO"] = mips.REG_LO
|
||
|
|
// Pseudo-registers.
|
||
|
|
register["SB"] = RSB
|
||
|
|
register["FP"] = RFP
|
||
|
|
register["PC"] = RPC
|
||
|
|
// Avoid unintentionally clobbering g using R30.
|
||
|
|
delete(register, "R30")
|
||
|
|
register["g"] = mips.REG_R30
|
||
|
|
|
||
|
|
registerPrefix := map[string]bool{
|
||
|
|
"F": true,
|
||
|
|
"FCR": true,
|
||
|
|
"M": true,
|
||
|
|
"R": true,
|
||
|
|
}
|
||
|
|
|
||
|
|
instructions := make(map[string]obj.As)
|
||
|
|
for i, s := range obj.Anames {
|
||
|
|
instructions[s] = obj.As(i)
|
||
|
|
}
|
||
|
|
for i, s := range mips.Anames {
|
||
|
|
if obj.As(i) >= obj.A_ARCHSPECIFIC {
|
||
|
|
instructions[s] = obj.As(i) + obj.ABaseMIPS
|
||
|
|
}
|
||
|
|
}
|
||
|
|
// Annoying alias.
|
||
|
|
instructions["JAL"] = mips.AJAL
|
||
|
|
|
||
|
|
return &Arch{
|
||
|
|
LinkArch: linkArch,
|
||
|
|
Instructions: instructions,
|
||
|
|
Register: register,
|
||
|
|
RegisterPrefix: registerPrefix,
|
||
|
|
RegisterNumber: mipsRegisterNumber,
|
||
|
|
IsJump: jumpMIPS,
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
func archMips64(linkArch *obj.LinkArch) *Arch {
|
||
|
|
register := make(map[string]int16)
|
||
|
|
// Create maps for easy lookup of instruction names etc.
|
||
|
|
// Note that there is no list of names as there is for x86.
|
||
|
|
for i := mips.REG_R0; i <= mips.REG_R31; i++ {
|
||
|
|
register[obj.Rconv(i)] = int16(i)
|
||
|
|
}
|
||
|
|
for i := mips.REG_F0; i <= mips.REG_F31; i++ {
|
||
|
|
register[obj.Rconv(i)] = int16(i)
|
||
|
|
}
|
||
|
|
for i := mips.REG_M0; i <= mips.REG_M31; i++ {
|
||
|
|
register[obj.Rconv(i)] = int16(i)
|
||
|
|
}
|
||
|
|
for i := mips.REG_FCR0; i <= mips.REG_FCR31; i++ {
|
||
|
|
register[obj.Rconv(i)] = int16(i)
|
||
|
|
}
|
||
|
|
for i := mips.REG_W0; i <= mips.REG_W31; i++ {
|
||
|
|
register[obj.Rconv(i)] = int16(i)
|
||
|
|
}
|
||
|
|
register["HI"] = mips.REG_HI
|
||
|
|
register["LO"] = mips.REG_LO
|
||
|
|
// Pseudo-registers.
|
||
|
|
register["SB"] = RSB
|
||
|
|
register["FP"] = RFP
|
||
|
|
register["PC"] = RPC
|
||
|
|
// Avoid unintentionally clobbering g using R30.
|
||
|
|
delete(register, "R30")
|
||
|
|
register["g"] = mips.REG_R30
|
||
|
|
// Avoid unintentionally clobbering RSB using R28.
|
||
|
|
delete(register, "R28")
|
||
|
|
register["RSB"] = mips.REG_R28
|
||
|
|
registerPrefix := map[string]bool{
|
||
|
|
"F": true,
|
||
|
|
"FCR": true,
|
||
|
|
"M": true,
|
||
|
|
"R": true,
|
||
|
|
"W": true,
|
||
|
|
}
|
||
|
|
|
||
|
|
instructions := make(map[string]obj.As)
|
||
|
|
for i, s := range obj.Anames {
|
||
|
|
instructions[s] = obj.As(i)
|
||
|
|
}
|
||
|
|
for i, s := range mips.Anames {
|
||
|
|
if obj.As(i) >= obj.A_ARCHSPECIFIC {
|
||
|
|
instructions[s] = obj.As(i) + obj.ABaseMIPS
|
||
|
|
}
|
||
|
|
}
|
||
|
|
// Annoying alias.
|
||
|
|
instructions["JAL"] = mips.AJAL
|
||
|
|
|
||
|
|
return &Arch{
|
||
|
|
LinkArch: linkArch,
|
||
|
|
Instructions: instructions,
|
||
|
|
Register: register,
|
||
|
|
RegisterPrefix: registerPrefix,
|
||
|
|
RegisterNumber: mipsRegisterNumber,
|
||
|
|
IsJump: jumpMIPS,
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
func archRISCV64() *Arch {
|
||
|
|
register := make(map[string]int16)
|
||
|
|
|
||
|
|
// Standard register names.
|
||
|
|
for i := riscv.REG_X0; i <= riscv.REG_X31; i++ {
|
||
|
|
name := fmt.Sprintf("X%d", i-riscv.REG_X0)
|
||
|
|
register[name] = int16(i)
|
||
|
|
}
|
||
|
|
for i := riscv.REG_F0; i <= riscv.REG_F31; i++ {
|
||
|
|
name := fmt.Sprintf("F%d", i-riscv.REG_F0)
|
||
|
|
register[name] = int16(i)
|
||
|
|
}
|
||
|
|
|
||
|
|
// General registers with ABI names.
|
||
|
|
register["ZERO"] = riscv.REG_ZERO
|
||
|
|
register["RA"] = riscv.REG_RA
|
||
|
|
register["SP"] = riscv.REG_SP
|
||
|
|
register["GP"] = riscv.REG_GP
|
||
|
|
register["TP"] = riscv.REG_TP
|
||
|
|
register["T0"] = riscv.REG_T0
|
||
|
|
register["T1"] = riscv.REG_T1
|
||
|
|
register["T2"] = riscv.REG_T2
|
||
|
|
register["S0"] = riscv.REG_S0
|
||
|
|
register["S1"] = riscv.REG_S1
|
||
|
|
register["A0"] = riscv.REG_A0
|
||
|
|
register["A1"] = riscv.REG_A1
|
||
|
|
register["A2"] = riscv.REG_A2
|
||
|
|
register["A3"] = riscv.REG_A3
|
||
|
|
register["A4"] = riscv.REG_A4
|
||
|
|
register["A5"] = riscv.REG_A5
|
||
|
|
register["A6"] = riscv.REG_A6
|
||
|
|
register["A7"] = riscv.REG_A7
|
||
|
|
register["S2"] = riscv.REG_S2
|
||
|
|
register["S3"] = riscv.REG_S3
|
||
|
|
register["S4"] = riscv.REG_S4
|
||
|
|
register["S5"] = riscv.REG_S5
|
||
|
|
register["S6"] = riscv.REG_S6
|
||
|
|
register["S7"] = riscv.REG_S7
|
||
|
|
register["S8"] = riscv.REG_S8
|
||
|
|
register["S9"] = riscv.REG_S9
|
||
|
|
register["S10"] = riscv.REG_S10
|
||
|
|
register["S11"] = riscv.REG_S11
|
||
|
|
register["T3"] = riscv.REG_T3
|
||
|
|
register["T4"] = riscv.REG_T4
|
||
|
|
register["T5"] = riscv.REG_T5
|
||
|
|
register["T6"] = riscv.REG_T6
|
||
|
|
|
||
|
|
// Go runtime register names.
|
||
|
|
register["g"] = riscv.REG_G
|
||
|
|
register["CTXT"] = riscv.REG_CTXT
|
||
|
|
register["TMP"] = riscv.REG_TMP
|
||
|
|
|
||
|
|
// ABI names for floating point register.
|
||
|
|
register["FT0"] = riscv.REG_FT0
|
||
|
|
register["FT1"] = riscv.REG_FT1
|
||
|
|
register["FT2"] = riscv.REG_FT2
|
||
|
|
register["FT3"] = riscv.REG_FT3
|
||
|
|
register["FT4"] = riscv.REG_FT4
|
||
|
|
register["FT5"] = riscv.REG_FT5
|
||
|
|
register["FT6"] = riscv.REG_FT6
|
||
|
|
register["FT7"] = riscv.REG_FT7
|
||
|
|
register["FS0"] = riscv.REG_FS0
|
||
|
|
register["FS1"] = riscv.REG_FS1
|
||
|
|
register["FA0"] = riscv.REG_FA0
|
||
|
|
register["FA1"] = riscv.REG_FA1
|
||
|
|
register["FA2"] = riscv.REG_FA2
|
||
|
|
register["FA3"] = riscv.REG_FA3
|
||
|
|
register["FA4"] = riscv.REG_FA4
|
||
|
|
register["FA5"] = riscv.REG_FA5
|
||
|
|
register["FA6"] = riscv.REG_FA6
|
||
|
|
register["FA7"] = riscv.REG_FA7
|
||
|
|
register["FS2"] = riscv.REG_FS2
|
||
|
|
register["FS3"] = riscv.REG_FS3
|
||
|
|
register["FS4"] = riscv.REG_FS4
|
||
|
|
register["FS5"] = riscv.REG_FS5
|
||
|
|
register["FS6"] = riscv.REG_FS6
|
||
|
|
register["FS7"] = riscv.REG_FS7
|
||
|
|
register["FS8"] = riscv.REG_FS8
|
||
|
|
register["FS9"] = riscv.REG_FS9
|
||
|
|
register["FS10"] = riscv.REG_FS10
|
||
|
|
register["FS11"] = riscv.REG_FS11
|
||
|
|
register["FT8"] = riscv.REG_FT8
|
||
|
|
register["FT9"] = riscv.REG_FT9
|
||
|
|
register["FT10"] = riscv.REG_FT10
|
||
|
|
register["FT11"] = riscv.REG_FT11
|
||
|
|
|
||
|
|
// Pseudo-registers.
|
||
|
|
register["SB"] = RSB
|
||
|
|
register["FP"] = RFP
|
||
|
|
register["PC"] = RPC
|
||
|
|
|
||
|
|
instructions := make(map[string]obj.As)
|
||
|
|
for i, s := range obj.Anames {
|
||
|
|
instructions[s] = obj.As(i)
|
||
|
|
}
|
||
|
|
for i, s := range riscv.Anames {
|
||
|
|
if obj.As(i) >= obj.A_ARCHSPECIFIC {
|
||
|
|
instructions[s] = obj.As(i) + obj.ABaseRISCV
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return &Arch{
|
||
|
|
LinkArch: &riscv.LinkRISCV64,
|
||
|
|
Instructions: instructions,
|
||
|
|
Register: register,
|
||
|
|
RegisterPrefix: nil,
|
||
|
|
RegisterNumber: nilRegisterNumber,
|
||
|
|
IsJump: jumpRISCV,
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
func archS390x() *Arch {
|
||
|
|
register := make(map[string]int16)
|
||
|
|
// Create maps for easy lookup of instruction names etc.
|
||
|
|
// Note that there is no list of names as there is for x86.
|
||
|
|
for i := s390x.REG_R0; i <= s390x.REG_R15; i++ {
|
||
|
|
register[obj.Rconv(i)] = int16(i)
|
||
|
|
}
|
||
|
|
for i := s390x.REG_F0; i <= s390x.REG_F15; i++ {
|
||
|
|
register[obj.Rconv(i)] = int16(i)
|
||
|
|
}
|
||
|
|
for i := s390x.REG_V0; i <= s390x.REG_V31; i++ {
|
||
|
|
register[obj.Rconv(i)] = int16(i)
|
||
|
|
}
|
||
|
|
for i := s390x.REG_AR0; i <= s390x.REG_AR15; i++ {
|
||
|
|
register[obj.Rconv(i)] = int16(i)
|
||
|
|
}
|
||
|
|
register["LR"] = s390x.REG_LR
|
||
|
|
// Pseudo-registers.
|
||
|
|
register["SB"] = RSB
|
||
|
|
register["FP"] = RFP
|
||
|
|
register["PC"] = RPC
|
||
|
|
// Avoid unintentionally clobbering g using R13.
|
||
|
|
delete(register, "R13")
|
||
|
|
register["g"] = s390x.REG_R13
|
||
|
|
registerPrefix := map[string]bool{
|
||
|
|
"AR": true,
|
||
|
|
"F": true,
|
||
|
|
"R": true,
|
||
|
|
}
|
||
|
|
|
||
|
|
instructions := make(map[string]obj.As)
|
||
|
|
for i, s := range obj.Anames {
|
||
|
|
instructions[s] = obj.As(i)
|
||
|
|
}
|
||
|
|
for i, s := range s390x.Anames {
|
||
|
|
if obj.As(i) >= obj.A_ARCHSPECIFIC {
|
||
|
|
instructions[s] = obj.As(i) + obj.ABaseS390X
|
||
|
|
}
|
||
|
|
}
|
||
|
|
// Annoying aliases.
|
||
|
|
instructions["BR"] = s390x.ABR
|
||
|
|
instructions["BL"] = s390x.ABL
|
||
|
|
|
||
|
|
return &Arch{
|
||
|
|
LinkArch: &s390x.Links390x,
|
||
|
|
Instructions: instructions,
|
||
|
|
Register: register,
|
||
|
|
RegisterPrefix: registerPrefix,
|
||
|
|
RegisterNumber: s390xRegisterNumber,
|
||
|
|
IsJump: jumpS390x,
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
func archWasm() *Arch {
|
||
|
|
instructions := make(map[string]obj.As)
|
||
|
|
for i, s := range obj.Anames {
|
||
|
|
instructions[s] = obj.As(i)
|
||
|
|
}
|
||
|
|
for i, s := range wasm.Anames {
|
||
|
|
if obj.As(i) >= obj.A_ARCHSPECIFIC {
|
||
|
|
instructions[s] = obj.As(i) + obj.ABaseWasm
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return &Arch{
|
||
|
|
LinkArch: &wasm.Linkwasm,
|
||
|
|
Instructions: instructions,
|
||
|
|
Register: wasm.Register,
|
||
|
|
RegisterPrefix: nil,
|
||
|
|
RegisterNumber: nilRegisterNumber,
|
||
|
|
IsJump: jumpWasm,
|
||
|
|
}
|
||
|
|
}
|